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gs815018/36ab-357/333/300/250 1m x 18, 512k x 36 18mb register-register late write sram 250 mhz?357 mhz 2.5 v v dd 1.5 v or 1.8 v hstl i/o 119-bump bga commercial temp industrial temp rev: 1.08 9/2008 1/25 ? 2003, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? register-register late write mode, pipelined read mode ? 2.5 v +200/?200 mv core power supply ? 1.5 v or 1.8 v hstl interface ? zq controlled programmable output drivers ? dual cycle deselect ? fully coherent read and write pipelines ? byte write operation (9-bit bytes) ? differential hstl clock inputs, k and k ? asynchronous output enable ? sleep mode via zz ? ieee 1149.1 jtag-complia nt serial boundary scan ? jedec-standard 11 9-bump bga package ? rohs-compliant 119-bum p bga package available family overview gs815018/36a are 18,874,368-bit (18mb) high performance srams. this family of wide, low voltage hstl i/o srams is designed to operate at the speeds needed to implement economical high performance cache systems. functional description because gs815018/36a are synchr onous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. write cy cles are internally self-timed and initiated by the risi ng edge of the clock input. this feature eliminates complex off-chip write pulse generation required by asynchronous srams and simplifies input signal timing. gs815018/36a support pipelined reads utilizing a rising-edge- triggered output register. they also utilize a dual cycle deselect (dcd) output deselect protocol. gs815018/36a are implemented with high performance hstl technology and are packaged in a 119-bump bga. mode control there are two mode control select pins (m1 and m2), which allow the user to set the correct read protocol for the design. the gs815018/36a support single clock pipeline mode, which directly affects the two mode control select pins. in order for the part to fuction correctly, an d as specified, m1 must be tied to v ss and m2 must be tied to v dd or v ddq . this must be set at power-up and should not be changed during operation. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. parameter synopsis -357 -333 -300 -250 unit pipeline cycle tkhqv 2.8 1.4 3.0 1.5 3.3 1.6 4.0 2.0 ns ns curr (x18) curr (x36) 600 650 550 600 500 550 450 500 ma ma
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 2/25 ? 2003, gsi technology gs815036 pinout?119-bump bg a?top view (package b) 1234567 a v ddq aancaav ddq b nc a a nc a a nc c nc a a v dd aanc d dq c dq c v ss zq v ss dq b dq b e dq c dq c v ss ss v ss dq b dq b f v ddq dq c v ss g v ss dq b v ddq g dq c d q c b c nc b b dq b dq b h dq c dq c v ss nc v ss dq b dq b j v ddq v dd v ref v dd v ref v dd v ddq k dq d dq d v ss ck v ss dq a dq a l dq d dq d b d ck b a dq a dq a m v ddq dq d v ss sw v ss dq a v ddq n dq d dq d v ss av ss dq a dq a p dq d dq d v ss av ss dq a dq a r nc a m1 v dd m2 a nc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 3/25 ? 2003, gsi technology gs815018 pinout?119-bump bg a?top view (package b) 1234567 a v ddq aancaav ddq b nc a a nc a a nc c nc a a v dd aanc d dq b nc v ss zq v ss dq a nc e nc dq b v ss ss v ss nc dq a f v ddq nc v ss g v ss dq a v ddq g nc d q b b b nc nc nc dq a h dq b n c v ss nc v ss dq a nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dq b v ss ck v ss nc dq a l dq b nc nc ck b a dq a nc m v ddq dq b v ss sw v ss nc v ddq n dq b nc v ss av ss dq a nc p nc dq b v ss av ss nc dq a r nc a m1 v dd m2 a nc t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 4/25 ? 2003, gsi technology read operations pipelined read a read cycle begins when th e ram captures logic 0 on ss and logic 1 on sw at the rising edge of k (and the falling edge of k ). address inputs captured on that clock edge are propigated into the ram, which delivers data to the input of the output register s. the second rising edge of k fires the output registers and releases read data to the output drivers. if g is held active low, the drivers drive the data onto the output pins. read data is sustained on the output pins as long as g is held low or until the next rising edge of k, at which point the outputs may update to new data or deselect, depending on what control command was registered at the second rising edge of k. gs815018/36 bga pin description symbol type description a i address inputs dq a dq b dq c dq d i/o data input and output pins b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq d i/os; active low nc ? no connect ck i clock input signal; active high ck i clock input signal; active low sw i write enable; active low g i output enable; active low zz i sleep mode control; active high m1 i read operation protocol select?sel ects register-register read operat ions; must be tied low in this device m2 i read operation protocol select?selects register-r egister read operations; must be tied high in this device zq i flxdrive-ii? output impedance control ss i synchronous select input tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock v ref i input reference voltage v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 5/25 ? 2003, gsi technology dual cycle deselect chip deselect ( ss = logic 1) is pipelined to the same degree as read data. therefore, a deselect comma nd entered on the rising edge of k is acted upon in response to the next rising edge of k. write operations write operations are initiated when the write enable input signal ( sw ) and chip select ( ss ) are captured at logic 0 on a rising edge of the k clock (and falling edge of the k clock). late write in late write mode the ram requires data in one rising clock edge later than the edge used to load address and control. late write protocol has been employed on srams designed for risc pr ocessor l2 cache applications an d in flow through mode nbt srams. byte write control the byte write enable inputs ( bx ) determine which bytes will be written. any combination of byte write enable control pins, including all or none, may be activated. a write cycle with no by te write inputs active is a write abort cycle. byte write cont rol inputs are captured by the same clock edge used to capture sw . flxdrive-ii? hstl output driver impedance control hstl i/o sigmarams are suppli ed with programmable impedan ce output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow the sram to monitor and adjust its output driver impedance. the value of rq must be 5x the valu e of the desired sram driver impedance. th e allowable range of rq to guarantee impedance matching with specified tolerance is between 150 and 300 . periodic readjustment of the output driver impedance occurs automati cally because driver impedance is affected by drifts in supply voltage and di e temperature. a clock cycle counter periodi cally triggers an impedance evaluation, resets and counts again. each impedance evaluation may move the output driver impedance level on e step at a time towards the optimum level. the output driver is implemented with discrete bi nary weighted impedance steps. the sram requires 32k start-up clock cycles, selected or deselected, after v dd reaches its operating range to reach it s programmed output driver impedance. example of x36 byte write truth table function sw ba bb bc bd read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort l h h h h
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 6/25 ? 2003, gsi technology register-register late write, pipelined read truth table ck zz ss sw b x g current operation dq (t n ) dq (t n+1 ) x 1 x x x x sleep (power down) mode hi-z hi-z 0 1 x x x deselect *** hi-z 0 0 1 x 1 read hi-z/ hi-z 0 0 1 x 0 read *** q(t n ) 0 0 0 0 x write all bytes *** d(t n ) 0 0 0 x x write bytes with b x = 0 *** d(t n ) 0 0 0 1 x write (abort) *** hi-z notes: 1. if one or more bx = 0, then b = ?t? else b = ?f?. 2. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?. 3. ?***? indicates that the dq input requirement/output state and cq output state are determi ned by the previous operation. 4. dqs are tristated in response to bank deselect, deselect, and write commands, one full cycle after the command is sampled. 5. cqs are tristated in response to bank deselect comm ands only, one full cycle after the command is sampled. 6. up to three (3) continue operations may be initiated after a re ad or write operation is initiated to burst transfer up to fou r (4) distinct pieces of data per single external address input. if a fourth (4th) continue operation is init iated, the internal address wraps back t o the initial exter - nal (base) address.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 7/25 ? 2003, gsi technology note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the recommended operating conditions, for an extended period of time, ma y affect reliability of this component. recommended oper ating conditions absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 3.13 v v ddq voltage in v ddq pins ?0.5 to 2.4 v v i/o voltage on i/o pins ?0.5 to v ddq + 0.5 ( 2.4 v max.) v v in voltage on other input pins ?0.5 to v ddq + 0.5 ( 2.4 v max.) v i in input current on any pin +/?20 ma dc i out output current on any i/o pin +/?20 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 2.3 2.5 2.7 v 1.8 v i/o supply voltage v ddq 1.7 1.8 1.95 v 1 1.5 v i/o supply voltage v ddq 1.4 1.5 1.6 v 1 ambient temperature (commercial range versions) t a 0 25 70 c ambient temperature (industrial range versions) t a ?40 25 85 c 2 note: 1. unless otherwise noted, all perfo rmance specifications quoted are evaluated for worst case at both 1.4 v v ddq 1.6 v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.95 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. the part number of industrial temperature range versions end t he character ?i?. unless otherwise noted, all performance speci fications quoted are evaluated for worst case in t he temperature range marked on the device.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 8/25 ? 2003, gsi technology hstl i/o dc input characteristics parameter symbol min typ max units notes dc input logic high v ih (dc) v ref + 100 ? v ddq + 300 mv dc input logic low v il (dc) ?300 ? v ref ? 100 mv dc clock input differential voltage v dif (dc) 100 ? v ddq + 300 mv 2 v ref dc voltage v ref (dc) v ddq /2 ? 0.1 ? v ddq /2 + 0.1 v 1 clock input voltag v ck (dc) ?300 ? v ddq + 300 v clock input commone mode voltage v cm (dc) 600 750 900 v notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. sram performance is a function of clock input differential voltage (v dif ). 3. to guarantee ac characteristics, v ih ,v il ,trise and tfall of inputs and clocks must be within 10% of each other. 4. for devices supplied with hstl i/o input buffers .compatible with both 1.8 v and 1.5 v i/o drivers. 5. see ac input definition drawing below. hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 200 ? mv 3,4 ac input logic low v il (ac) ? v ref ? 200 mv 3,4 ac clock input differential voltage v dif (ac) 800 ? mv 2,3 v ref peak to peak ac voltage v ref (ac) ? 5% v ref (dc) mv 1 notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. sram performance is a function of clock input differential voltage (v dif ). the ram can be operated with a single ended clocking with either ck or ck tied to v ref . 3. to guarantee ac characteristics, v ih ,v il ,trise and tfall of inputs and clocks must be within 10% of each other. 4. for devices supplied with hstl i/o input buffers .compatible with both 1.8 v and 1.5 v i/o drivers. 5. see ac input definition drawing below.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 9/25 ? 2003, gsi technology hstl i/o ac input definitions differential voltage and common mode voltage v ih (dc) v ref v il (dc) v ddq v ih (ac) v ih (ac) v ss common mode and di fferential voltage -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 20406080100120 time volts k k# vcm vdif vcm
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 10/25 ? 2003, gsi technology note: this parameter is sample tested. capacitance (t a = 25 o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions max. unit input capacitance c in v in = 0 v 4 pf output capacitance c out v out = 0 v 5 pf output capacitance (clock) c in(ck) v in = 0 v 5 pf ac test conditions parameter conditions input high level 1.25 v input low level 0.25 v input rise/fall time (10% to 90%) 0.5 ns/0.5 ns input reference level v ddq /2 clock input reference level differential cross point output reference level v ddq /2 clock (v dif ) 0.75 v clock (v cm ) 0.75 v v ddq 1.5 v rq 250 20% tkc v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkc v dd + 1.0 v 50% v dd v il
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 11/25 ? 2003, gsi technology ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v ddq ?1 ua 1 ua ? zq, mch, mcl, ep2, ep3 pin input current i inm v in = 0 to v ddq ?100 ua 1 ua ? output leakage current i ol output disable, v out = 0 to v ddq ?1 ua 1 ua ? operating currents parameter symbol -357 -333 -300 -250 test conditions 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current x36 i dd 650 ma 660 ma 600 ma 610 ma 550 ma 560 ma 500 ma 510 ma ss v il max. tkhkh tkhkh min. all other inputs v il v in v ih x18 i dd 600 ma 610 ma 550 ma 560 ma 500 ma 510 ma 450 ma 460 ma hstl deselect current i dd3 150 ma 160 ma 150 ma 160 ma 150 ma 160 ma 150 ma 160 ma device deselected all inputs v ss + 0.10 v v in v dd ? 0.10 v dq v ddq /2 50 50 50 50 v ddq /2 v ddq /2 25 5pf 5pf device under test v ddq = 1.5 v zq rq = 250
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 12/25 ? 2003, gsi technology ac electrical characteristics parameter symbol -357 -333 -300 -250 unit notes min max min max min max min max clock cycle time tkhkh 2.8 ? 3.0 ? 3.3 ? 4.0 ? ns ? clock high time tkhkl 1.1 ? 1.2 ? 1.3 ? 1.5 ? ns ? clock low time tklkh 1.1 ? 1.2 ? 1.3 ? 1.5 ? ns ? clock high to output low-z tkhqx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 1 clock high to output valid tkhqv ? 1.4 ? 1.5 1.6 ? 2.0 ns ? clock high to output invalid tkhqx 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns ? clock high to output high-z tkhqz ? 1.4 ? 1.5 1.6 ? 2.0 ns 1 address valid to clock high tavkh 0.5 ? 0.6 ? 0.7 ? 0.8 ? ns ? clock high to address don?t care tkhax 0.4 ? 0.4 ? 0.4 ? 0.5 ? ns ? enable valid to clock high tevkh 0.5 ? 0.6 ? 0.7 ? 0.8 ? ns ? clock high to enable don?t care tkhex 0.4 ? 0.4 ? 0.4 ? 0.5 ? ns ? write valid to clock high twvkh 0.5 ? 0.6 ? 0.7 ? 0.8 ? ns ? clock high to write don?t care tkhwx 0.4 ? 0.4 ? 0.4 ? 0.5 ? ns ? byte write valid to clock high tbvkh 0.5 ? 0.6 ? 0.7 ? 0.8 ? ns ? clock high to byte write don?t care tkhbx 0.4 ? 0.4 ? 0.4 ? 0.5 ? ns ? data in valid to clock high tdvkh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns ? clock high to data in don?t care tkhdx 0.4 ? 0.4 ? 0.4 ? 0.5 ? ns ? output enable low to output data valid tglqv ? 1.4 ? 1.5 1.6 ? 2.0 ns ? output enable low to output data low-z tglqx 0 ? 0 ? 0 ? 0 ? ns ? output enable high to output data high-z tghqz ? 1.4 ? 1.5 1.6 ? 2.0 ns ? sleep mode enable time tzze ? 15 ? 15 ? 15 ? 15 ns ? sleep mode recovery time tzzr 20 ? 20 ? 20 ? 20 ? ns ? notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 13/25 ? 2003, gsi technology g controlled read-write note: k is not shown; assumes k tied to v ref or out of phase with k ss controlled read-write note: k is not shown; assumes k tied to v ref or out of phase with k read a1 read a2 read a0 write a3 write a4 read a5 read a4 read a6 read a7 khqv khqx1 khdx dvkh ghqz khqx glqv glqx tkhwx twvkh tkhwx twvkh tkhax tavkh klkh klkh khkl khkl khkh khkh a1 a2 a3 a4 a5 a4 a6 a7 q1 q2 d3 d4 q5 q4 a0 q6 k a g sw bwx dqn read a1 read a2 deselect write a3 write a4 read a5 read a4 read a6 read a7 khqx tkhdx tdvkh khqz khqv khqx1 tkhbx tbvkh tkhwx twvkh tkhex tevkh tkhax tavkh klkh klkh khkl khkl khkh khkh a1 a2 a3 a4 a5 a4 a6 a7 q1 q2 d3 d4 q5 q4 k a ss sw bwx dqn
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 14/25 ? 2003, gsi technology zz timing note: k is not shown; assumes k tied to v ref or out of phase with k jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. read a1 read a2 deselect clock is a don't care during sleep moderead a1 read a2 read a3 khqx khqv zze khqx1 zzr tkhwx twvkh tkhex tevkh tkhax tavkh klkh klkh khkl khkl khkh khkh a1 a2 a1 a2 a3 q1 q2 q1 begin isb k a ss sw swx zz dqn
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 15/25 ? 2003, gsi technology jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are select ed (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 16/25 ? 2003, gsi technology jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. instruction register id code register boundary scan register 0 1 2 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 17/25 ? 2003, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandator y for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instructi on register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 x x x x 0 0 0 x 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 x x x x 0 0 0 x 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 18/25 ? 2003, gsi technology jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 19/25 ? 2003, gsi technology typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan re gister between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 20/25 ? 2003, gsi technology jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v 1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 2.5 v test port input high voltage v ihj2 0.6 * v ddq2 v ddq2 +0.3 v 1 2.5 v test port input low voltage v ilj2 ? 0.3 0.3 * v ddq2 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj 1.7 ? v 5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v 5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 1 v > vi < v ddn +1 v not to exceed 3.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddq 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddq 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 30pf * jtag port ac test load * distributed test jig capacitance
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 21/25 ? 2003, gsi technology jtag port timing diagram jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns tth tts ttkq tth tts tth tts ttkl ttkl ttkh ttkh ttkc ttkc tck tdi tms tdo parallel sram input
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 22/25 ? 2003, gsi technology package dimensions?119-bump fpbga (package b, variation 2 ) a b c d e f g h j k l m n p r t u 1 2 3 4 5 6 7 7 6 5 4 3 2 1 a1 top view a1 bottom view 1.27 7.62 1.27 20.32 140.10 220.10 b a 0.20(4x) ?0.10 ?0.30 c c a b s s ?0.60~0.90 (119x) c seating plane 0.15 c 0.50~0.70 1.86.0.13 a b c d e f g h j k l m n p r t u s s
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 23/25 ? 2003, gsi technology ordering information org part number type speed (mhz) t a 1m x 18 gs815018ab-357 register-register late write sram 357 mhz c 1m x 18 gs815018ab-333 register-register late write sram 333 mhz c 1m x 18 gs815018ab-300 register-register late write sram 300 mhz c 1m x 18 GS815018AB-250 register-register late write sram 250 mhz c 512k x 36 gs815036ab-357 register-register late write sram 357mhz c 512k x 36 gs815036ab-333 register-register late write sram 333 mhz c 512k x 36 gs815036ab-300 register-register late write sram 300 mhz c 512k x 36 gs815036ab-250 register-register late write sram 250 mhz c 1m x 18 gs815018ab-357i register-register late write sram 357 mhz i 1m x 18 gs815018ab-333i register-register late write sram 333 mhz i 1m x 18 gs815018ab-300i register-register late write sram 300 mhz i 1m x 18 GS815018AB-250i register-register late write sram 250 mhz i 512k x 36 gs815036ab-357i register-register late write sram 357 mhz i 512k x 36 gs815036ab-333i register-register late write sram 333 mhz i 512k x 36 gs815036ab-300i register-register late write sram 300 mhz i 512k x 36 gs815036ab-250i register-register late write sram 250 mhz i 1m x 18 gs815018agb-357 rohs-compliant register-register late write sram 357 mhz c 1m x 18 gs815018agb-333 rohs-compliant register-register late write sram 333 mhz c 1m x 18 gs815018agb-300 rohs-compliant register-register late write sram 300 mhz c 1m x 18 gs815018agb-250 rohs-compliant register-register late write sram 250 mhz c 512k x 36 gs815036agb-357 rohs-compliant register-register late write sram 357mhz c 512k x 36 gs815036agb-333 rohs-compliant register-register late write sram 333 mhz c 512k x 36 gs815036agb-300 rohs-compliant register-register late write sram 300 mhz c 512k x 36 gs815036agb-250 rohs-compliant register-register late write sram 250 mhz c 1m x 18 gs815018agb-357i rohs-compliant register-register late write sram 357 mhz i 1m x 18 gs815018agb-333i rohs-compliant register-register late write sram 333 mhz i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs815036ab -300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 24/25 ? 2003, gsi technology 1m x 18 gs815018agb-300i rohs-compliant register-register late write sram 300 mhz i 1m x 18 gs815018agb-250i rohs-compliant register-register late write sram 250 mhz i 512k x 36 gs815036agb-357i rohs-compliant register-register late write sram 357 mhz i 512k x 36 gs815036agb-333i rohs-compliant register-register late write sram 333 mhz i 512k x 36 gs815036agb-300i rohs-compliant register-register late write sram 300 mhz i 512k x 36 gs815036agb-250i rohs-compliant register-register late write sram 250 mhz i ordering information org part number type speed (mhz) t a notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs815036ab -300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.
gs815018/36ab-357/333/300/250 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.08 9/2008 25/25 ? 2003, gsi technology 18mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 8150xxa_r1 ? creation of new datasheet 8150xxa_r1; 8150xxa_r1_01 content/format ? corrected l3 from vss to nc ? updated en tire format ? placed corrected bga diagram in document 8150xxa_r1_01; 8150xxa_r1_02 content/format ? updated format ? added variation information to 119 bga mechanical drawing 8150xxa_r1_02; 8150xxa_r1_03 content ? updated ac characteristics table ? updated /g controlled read-write timing diagram ? updated jtag port rec. op con & dc char table 8150xxa_r1_03; 8150xxa_r1_04 content ? pb-free information added 8150xxa_r1_04; 8150xxa_r1_05 content ? changed v dd to max 3.6 v for 8150xxa 8150xxa_r1_05; 8150xxa_r1_06 content ? updated abs max section ? changed all pb-free refe rences to rohs-compliant 8150xxa_r1_06; 8150xxa_r1_07 content ? updated power supplies table on page 7 8150xxa_r1_07; 8150xxa_r1_08 content ? updated for mp status

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